In semiconductor manufacturing process, along with the advance in IC manufacturing process and improvement in integration degree of chips, the copper interconnection has replaced the aluminum interconnection as the main tridimensional interconnection in VLSI. As the substitute of aluminum interconnection, the copper interconnection has many advantages: firstly, the resistivity of copper is lower than that of aluminum, and the coupled delay of copper subsequent-interconnection is also less than that of aluminum subsequent-interconnection, which is propitious to promote the device performance and reduce the power consumption. Secondly, since the cross section area of the copper interconnection is less than that of the aluminum interconnection, the parasitical capacitance between the adjacent wirings is reduced under the same current condition, which decreases the signal crosstalk. Furthermore, the resistance to electromigration of copper is better than that of aluminum, which would avoid the problem of forming voids in the interconnect, and the device reliability can be enhanced. In conclusion, the application of the copper interconnection can increase the integration degree of chips, the device density, the clock frequency, and reduce the power consumption and cost.
Due to the difficulties in etching copper, dual-Damascene process is generally introduced in the copper interconnection conventionally. The dual-Damascene process comprises the following steps:
Step 1: depositing a thin etch stop layer;
Step 2: depositing a insulating layer with certain thickness on the etch stop layer;
Step 3: applying corresponding photolithography and etching process to form integral vias and trenches;
Step 4: sputtering a diffusion barrier layer and depositing a copper seed layer using PVD;
Step 5: electroplating on the copper seed layer to form the copper interconnects;
Step 6: applying annealing and chemical and mechanical polishing (CMP) to planarize the copper electroplating layer and rinsing.
Repeating the processes including step 1 to step 6 mentioned above, a stack of multiple copper interconnection layers can be formed. According to Faraday's law, in the process of electroplating, electrolytic solution containing sulfate electrolyte is utilized, and electrical power source is applied to the anode (copper) and the cathode (silicon wafer) of the electroplating bath to form an electric field and electric current in the solution. The copper losing electrons at the anode may transfer to copper ions, and copper ions adjacent to the cathode may transfer to copper atoms by gaining electrons on the silicon wafer surface and be deposited on the silicon wafer surface. Under the application of an electric field, the copper ions may move directionally from the anode to the cathode and compensate the concentration depletion adjacent to the cathode. By controlling the deposition of the copper electroplating film through current regulation and distribution, a compact and homogeneous distributed copper layer without cavities, gaps or other defects can be deposited on the silicon wafer.
In order to form a copper film having better consistency and uniformity, the current densities for the whole copper interconnection layer surface are required to have less difference in the electroplating process. Due to the shrinking in IC critical dimension and the increase in depth-width ratio of the trenches, the filling performance of the trenches, the quality of the electroplated layers and the topography of the copper interconnection layer after electroplating can be affected by a plurality of factors, such as: the post-etch profile, the thickness of the seed layer, the main salt concentration, the pH value, the current parameter, the temperature, and organic additives (accelerator, suppressor and leverler), etc. Wherein, the filling performance is closely related to the composition and the concentration of the organic additives. The first consideration for optimizing the electroplating process is how to promote the properties related to conductivity and reliability such as filling performance, compactness, crystal grain size and defect. The control of the electroplated topography may not be the key point of electroplating process in the past.
However, as known to all, the CMP process after electroplating is the indispensable technique for implementing copper subsequent-interconnection. As shown in FIG. 1, which is a sectional view of the copper interconnection layer to show the topography of the copper interconnection layer surface after copper CMP, dishing and erosion are the main defects induced by copper CMP (for simplicity, only one copper interconnection layer is illustrated herein). Such defects could affect the planarization of the chip surface and reduce the effective thickness of the copper wirings which may result in the increase in the resistivity of the copper wirings. Furthermore, due to the accumulation of the dishing and erosion defects, copper residues may be formed in the subsequent metal interconnection layer, which may result in short circuit between the copper wirings and decrease in the chip yield or even chip rejection. Therefore, reducing dishing and erosion in copper CMP is very important to the copper interconnection technique. Dishing and erosion in copper CMP can be caused by the following two aspects.
In one aspect, during the over-polishing process of copper CMP, copper is exposed in the interconnection regions of the copper interconnection layer surface, and the insulating dielectric and the diffusion barrier layer thereon are exposed in the isolation regions. The removal rates during the CMP process are different according to different materials. The ratio of the removal rate of one material to the removal rate of another material is called the “selectivity ratio”. Generally, the removal rate of copper is higher than that of the insulating dielectric and the diffusion barrier layer thereon, thus the removal of the copper in the copper interconnection region is more than the removal in the insulating dielectric region. Dishing and erosion can be reduced by using proper slurry and pad, and optimizing the process condition of CMP.
In the other aspect, as shown in FIG. 2, due to the loading effects during the process of electroplating, the copper surface formed by electroplating before copper CMP is not planarized. The unplanarization can be caused by the native uneven topography of the trench structure as well as the special effect of the electroplating process such as the over-electroplating effect, which may cause the copper electroplated thicker in dense region of the wirings. As shown in FIG. 3, the typical topography differences in different regions after electroplating can be denoted clearly by surface scanning through the Atom Force Microscope (AFM). The surface topography after electroplating is determined by the design rules and the layout, and the surface topography of different regions may be different, thus the copper need to be removed in the respective regions are different accordingly and the CMP process can be affected. Furthermore, the surface topography of the copper interconnection layer after electroplating may also affect the CMP process directly in another aspect. Due to the topography unevenness, the local pressures subjected by the respective regions during the CMP process are different, which may result in different time span for removing the copper with the same thickness over the insulating dielectric/diffusion barrier layer (Ta/TaN) in the different regions. As shown in FIG. 4, the change of the surface topography of the copper interconnection layer during the actual removal process is illustrated. Different time span means that some regions may be subjected to a shorter time span of removal, while some regions may be subjected to a longer time span of removal, which is prone to form dishing and erosion. As can be seen, the electroplated surface topography may affect CMP process in many ways, and dishing and erosion are more likely to be formed. Although the unevenness of the electroplated surface can be eliminated by designing the pattern layout properly, such as adding redundant metal, so as to reduce dishing and erosion, however, it may be limited by the design rules and the electricity requirement of the device and may not be effective always.